Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7947980 | Non-volatile memory cell with charge storage element and method of programming | Shahin Toutounchi, James Karp, Jeongheon Jeong, Michael J. Hart | 2011-05-24 |
| 7687797 | Three-terminal non-volatile memory element with hybrid gate dielectric | James Karp, Daniel Gitlin, Shahin Toutounchi, Jongheon Jeong | 2010-03-30 |
| 7544968 | Non-volatile memory cell with charge storage element and method of programming | Shahin Toutounchi, James Karp, Jongheon Jeong, Michael J. Hart | 2009-06-09 |
| 7450431 | PMOS three-terminal non-volatile memory element and method of programming | James Karp, Jongheon Jeong, Shahin Toutounchi | 2008-11-11 |
| 7420842 | Method of programming a three-terminal non-volatile memory element using source-drain bias | Shahin Toutounchi, James Karp, Jongheon Jeong | 2008-09-02 |
| 6687157 | Circuits and methods for identifying a defective memory cell via first, second and third wordline voltages | Ping-Chen Liu, Kenneth Miu | 2004-02-03 |
| 6525973 | Automatic bitline-latch loading for flash prom test | Farshid Shokouhi | 2003-02-25 |
| 6388946 | Circuit and method for incrementally selecting word lines | Phillip H. McGibney | 2002-05-14 |
| 6285584 | Method to implement flash memory | Anders T. Dejenfelt, Qi Lin, Robert Olah | 2001-09-04 |
| 6272060 | Shift register clock scheme | Ben Sheen | 2001-08-07 |
| 6249458 | Switching circuit for transference of multiple negative voltages | Farshid Shokouhi, Ben Sheen | 2001-06-19 |
| 6233177 | Bitline latch switching circuit for floating gate memory device requiring zero volt programming voltage | Farshid Shokouhi | 2001-05-15 |
| 6212103 | Method for operating flash memory | Anders T. Dejenfelt, Qi Lin, Robert Olah | 2001-04-03 |
| 6112322 | Circuit and method for stress testing EEPROMS | Phillip H. McGibney | 2000-08-29 |
| 5671234 | Programmable input/output buffer circuit with test capability | Christopher E. Phillips, Joseph G. Nolan, III, Laurence H. Cooke | 1997-09-23 |
| 5652527 | Input-output circuit for increasing immunity to voltage spikes | Christopher E. Phillips, Joseph G. Nolan, III, Laurence H. Cooke | 1997-07-29 |
| 5629636 | Ram-logic tile for field programmable gate arrays | — | 1997-05-13 |
| 5534798 | Multiplexer with level shift capabilities | Christopher E. Phillips, Joseph G. Nolan, III, Laurence H. Cooke | 1996-07-09 |
| 5465055 | RAM-logic tile for field programmable gate arrays | — | 1995-11-07 |
| 5453696 | Embedded fuse resistance measuring circuit | William R. Becker | 1995-09-26 |
| 5299150 | Circuit for preventing false programming of anti-fuse elements | Douglas C. Galbraith, Esmat Z. Hamdy, Abdelshafy A. Eltoukhy | 1994-03-29 |
| 5286992 | Low voltage device in a high voltage substrate | Douglas C. Galbraith, Abdelshafy A. Eltoukhy | 1994-02-15 |
| 5221865 | Programmable input/output buffer circuit with test capability | Christopher E. Phillips, Joseph G. Nolan, III, Laurence H. Cooke | 1993-06-22 |
| 4918341 | High speed static single-ended sense amplifier | Douglas C. Galbraith | 1990-04-17 |