Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4774202 | Memory device with interconnected polysilicon layers and method for making | David S. Pan, Kanak C. Sarma, Mark A. Halfacre, Alexander H. Owens | 1988-09-27 |
| 4706102 | Memory device with interconnected polysilicon layers and method for making | David S. Pan, Kanak C. Sarma, Mark A. Halfacre, Alexander H. Owens | 1987-11-10 |
| 4701780 | Integrated verticle NPN and vertical oxide fuse programmable memory cell | Kevin T. Hankins, Mark W. Michael, Jay D. Moser, Sr. | 1987-10-20 |
| 4694430 | Logic controlled switch to alternate voltage sources | — | 1987-09-15 |
| 4635345 | Method of making an intergrated vertical NPN and vertical oxide fuse programmable memory cell | Kevin T. Hankins, Mark W. Michael | 1987-01-13 |
| 4612630 | EEPROM margin testing design | — | 1986-09-16 |