Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12155204 | Method and system for fin-based voltage clamp | Andrew J. Walker, Clifford Drowley, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Joseph S. Tandingan | 2024-11-26 |
| 12125914 | Method and system for fabrication of a vertical fin-based field effect transistor | Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui | 2024-10-22 |
| 11735671 | Method and system for fabrication of a vertical fin-based field effect transistor | Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui | 2023-08-22 |
| 11728415 | Method for regrown source contacts for vertical gallium nitride based FETS | Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi | 2023-08-15 |
| 11335810 | Method and system for fabrication of a vertical fin-based field effect transistor | Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui | 2022-05-17 |
| 9842629 | Memory cell array latchup prevention | Ravindra M. Kapre, Helmut Puchner, Nayan Patel | 2017-12-12 |
| 8837245 | Memory cell array latchup prevention | Ravlndra Kapre | 2014-09-16 |
| 8493804 | Memory cell array latchup prevention | Ravindra M. Kapre | 2013-07-23 |
| 8045410 | Memory cell array | Ravindra M. Kapre | 2011-10-25 |
| 7773442 | Memory cell array latchup prevention | Ravindra M. Kapre | 2010-08-10 |
| 6831346 | Buried layer substrate isolation in integrated circuits | Gabriel Li, Kenelm G. D. Murray, Jose Arreola, K. Nirmal Ratnakumar | 2004-12-14 |
| 6773975 | Formation of a shallow trench isolation structure in integrated circuits | Krishnaswamy Ramkumar, Sundar Narayanan | 2004-08-10 |
| 6734108 | Semiconductor structure and method of making contacts in a semiconductor structure | Bo Jin, Jianmin Qiao | 2004-05-11 |
| 5897371 | Alignment process compatible with chemical mechanical polishing | Kuantai Yeh, Ahmad Chatila | 1999-04-27 |