Issued Patents All Time
Showing 1–25 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381159 | Method and system for fabricating fiducials for processing of semiconductor devices | David A. DeMuynck, Subhash Srinivas Pidaparthi, Sharlene A. Wilson, Karthik Suresh Arulalan, Mark Curtice +1 more | 2025-08-05 |
| 12334352 | Method and system for etch depth control in III-V semiconductor devices | Wayne Chen, Andrew P. Edwards, Subhash Srinivas Pidaparthi | 2025-06-17 |
| 12272654 | Method and system for fabricating fiducials using selective area growth | Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards | 2025-04-08 |
| 12274086 | Fabrication method for JFET with implant isolation | Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano | 2025-04-08 |
| 12262557 | Methods and systems to improve uniformity in power FET arrays | Andrew P. Edwards, Hao Cui, Subhash Srinivas Pidaparthi | 2025-03-25 |
| 12224344 | Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors | Andrew P. Edwards, Hao Cui, Subhash Srinivas Pidaparthi, Michael D. Craven, David A. DeMuynck | 2025-02-11 |
| 12155204 | Method and system for fin-based voltage clamp | Andrew J. Walker, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Shahin Sharifzadeh, Joseph S. Tandingan | 2024-11-26 |
| 12136645 | Coupled guard rings for edge termination | Andrew P. Edwards, Hao Cui, Subhash Srinivas Pidaparthi | 2024-11-05 |
| 12125914 | Method and system for fabrication of a vertical fin-based field effect transistor | Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh | 2024-10-22 |
| 12113101 | Method and system of junction termination extension in high voltage semiconductor devices | Subhash Srinivas Pidaparthi, Andrew P. Edwards, Kedar Patel | 2024-10-08 |
| 12080757 | Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices | Hao Cui | 2024-09-03 |
| 11996407 | Self-aligned isolation for self-aligned contacts for vertical FETS | Hao Cui, Andrew P. Edwards, Subhash Srinivas Pidaparthi | 2024-05-28 |
| 11948801 | Method and system for etch depth control in III-V semiconductor devices | Wayne Chen, Andrew P. Edwards, Subhash Srinivas Pidaparthi | 2024-04-02 |
| 11935838 | Method and system for fabricating fiducials using selective area growth | Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards | 2024-03-19 |
| 11929440 | Fabrication method for JFET with implant isolation | Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano | 2024-03-12 |
| 11916134 | Regrowth uniformity in GaN vertical devices | Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards | 2024-02-27 |
| 11824086 | Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices | Hao Cui | 2023-11-21 |
| 11735671 | Method and system for fabrication of a vertical fin-based field effect transistor | Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh | 2023-08-22 |
| 11728415 | Method for regrown source contacts for vertical gallium nitride based FETS | Andrew P. Edwards, Subhash Srinivas Pidaparthi, Shahin Sharifzadeh | 2023-08-15 |
| 11637209 | JFET with implant isolation | Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano | 2023-04-25 |
| 11601106 | Thin-film bulk acoustic resonator and semiconductor apparatus comprising the same | Herb He Huang, Jiguang Zhu, Halting Li | 2023-03-07 |
| 11575358 | Thin-film bulk acoustic resonator and semiconductor apparatus comprising the same | Herb He Huang, Jiguang Zhu, Haiting Li | 2023-02-07 |
| 11575000 | Super-junction based vertical gallium nitride JFET power devices | Hao Cui | 2023-02-07 |
| 11562980 | Wafer-level package structure | Hailong LUO | 2023-01-24 |
| 11450582 | Wafer-level package structure | Hailong LUO | 2022-09-20 |