Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11876090 | ESD protection circuit | David Michael Rogers, Eric N. Mann, Eric Lee Swindlehurst, Toru Miyamae, Timothy Williams +6 more | 2024-01-16 |
| 11581729 | Combined positive and negative voltage electrostatic discharge (ESD) protection clamp with cascoded circuitry | David Michael Rogers, Henry H. Yuan, Mimi Qian, Myeongseok Lee, Yan Yi +2 more | 2023-02-14 |
| 11521962 | ESD protection circuit | David Michael Rogers, Eric N. Mann, Eric Lee Swindlehurst, Toru Miyamae, Timothy Williams +6 more | 2022-12-06 |
| 11361826 | Asymmetric pass field-effect transistor for nonvolatile memory | Venkatraman Prabhakar | 2022-06-14 |
| 10706937 | Asymmetric pass field-effect transistor for non-volatile memory | Venkatraman Prabhakar | 2020-07-07 |
| 10418110 | Asymmetric pass field-effect transistor for nonvolatile memory | Venkatraman Prabhakar | 2019-09-17 |
| 10217639 | Method of forming drain extended MOS transistors for high voltage circuits | Igor G. Kouznetsov, Gyu-Chul Kim | 2019-02-26 |
| 10020060 | Asymmetric pass field-effect transistor for nonvolatile memory | Venkatraman Prabhakar | 2018-07-10 |
| 9589652 | Asymmetric pass field-effect transistor for non-volatile memory | Venkatraman Prabhakar | 2017-03-07 |
| 9472511 | ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage | Roger Bettman, Sai Prashanth Dhanraj, Dung Si Ho, Leo F Luquette, Jr., Iman Rezanezhad Gatabi +1 more | 2016-10-18 |
| 9123642 | Method of forming drain extended MOS transistors for high voltage circuits | Igor G. Kouznetsov, Gyu-Chul Kim | 2015-09-01 |
| 7592661 | CMOS embedded high voltage transistor | Helmut Puchner | 2009-09-22 |
| 6323091 | Method of forming semiconductor memory device with LDD | Timothy K. Carns | 2001-11-27 |