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Low standby power with fast turn on method for non-volatile memory devices |
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Low standby power with fast turn on method for non-volatile memory devices |
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Low standby power with fast turn on method for non-volatile memory devices |
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Systems, methods, and devices for parallel read and write operations |
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ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage |
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Content addressable memory (CAM) cell bit line architecture |
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Content addressable memory (CAM) cell bit line architecture |
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CPLD high speed path |
— |
2002-11-26 |
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1997-02-04 |
