Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12348188 | Feedforward cancellation circuit | Bo Sun, Jafar Savoj | 2025-07-01 |
| 12028075 | Data detection on serial communication links | Vishal Varma, Dhaval Shah, Jose A. Tierno, Sumeet Gupta | 2024-07-02 |
| 12028077 | Phase detector circuit for multi-level signaling | Wenbo Liu, Gokce Gurun, Ajay M. Rao | 2024-07-02 |
| 12021577 | Serial communication link driver circuit with switchable shunt circuit | Yudong Zhang, Charles L. Wang | 2024-06-25 |
| 11770274 | Receiver with half-rate sampler circuits | Wing Liu | 2023-09-26 |
| 11757681 | Serial data receiver circuit with dither assisted equalization | Jose A. Tierno, Haiming Jin, Brian S. Leibowitz, Chintan S. Thakkar | 2023-09-12 |
| 11664809 | Serial data receiver with sampling clock skew compensation | Jaeduk Han, Wenbo Liu, Wing Liu, Ming Chen, Vishal Varma +3 more | 2023-05-30 |
| 11619959 | Low dropout regulator with feedforward power supply noise rejection circuit | Gokce Gurun, Wenbo Liu | 2023-04-04 |
| 11586240 | On-chip supply ripple tolerant clock distribution | Bo Sun, Brian S. Leibowitz, Jafar Savoj | 2023-02-21 |
| 11392163 | On-chip supply ripple tolerant clock distribution | Bo Sun, Brian S. Leibowitz, Jafar Savoj | 2022-07-19 |
| 11063600 | Multi-stage clock generator using mutual injection for multi-phase generation | Wenbo Liu, Wei-Ming Lee | 2021-07-13 |
| 11023403 | Chip to chip interface with scalable bandwidth | Jafar Savoj, Jose A. Tierno, Brian S. Leibowitz, Pradeep Trivedi, Gin Yee +1 more | 2021-06-01 |
| 10972107 | Serial data receiver with sampling clock skew compensation | Jaeduk Han, Wenbo Liu, Wing Liu, Ming Chen, Vishal Varma +3 more | 2021-04-06 |
| 10521391 | Chip to chip interface with scalable bandwidth | Jafar Savoj, Jose A. Tierno, Brian S. Leibowitz, Pradeep Trivedi, Gin Yee +1 more | 2019-12-31 |
| 10277230 | Jitter reduction in clock and data recovery circuits | Wenbo Liu, Ming Chen | 2019-04-30 |
| 9787509 | Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample | Lizhi Zhong, Vishnu Balan, Arif Amin | 2017-10-10 |
| 9231802 | Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample | Lizhi Zhong, Vishnu Balan, Arif Amin | 2016-01-05 |
| 9083577 | Sampler circuit for a decision feedback equalizer and method of use thereof | Vishnu Balan, Arif Amin | 2015-07-14 |
| 8451064 | Voltage-controlled oscillator module having adjustable oscillator gain and related operating methods | Emerson S. Fang, Sanjeev Aggarwal | 2013-05-28 |
| 8269533 | Digital phase-locked loop | Emerson S. Fang | 2012-09-18 |
| 7826998 | System and method for measuring the temperature of a device | Babak Taheri, Gopal Patil | 2010-11-02 |
| 7817761 | Test techniques for a delay-locked loop receiver interface | Meei-Ling Chiang, Dwight K. Elvey, Emerson S. Fang | 2010-10-19 |
| 7750711 | Phase select circuit with reduced hysteresis effect | Meei-Ling Chiang, Emerson S. Fang | 2010-07-06 |
| 7545190 | Parallel multiplexing duty cycle adjustment circuit with programmable range control | Meei-Ling Chiang, Emerson S. Fang | 2009-06-09 |
| 7355489 | High gain, high frequency CMOS oscillator circuit and method | — | 2008-04-08 |