Meei-Ling Chiang — 14 Patents at AMD

Meei-Ling Chiang has been granted 14 US patents while listed as an inventor at AMD. The first was granted in 2001 and the most recent in March 2025. Meei-Ling Chiang ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Meei-Ling Chiang in Cupertino, CA, US.

Patents per Year

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Showing 1–14 of 14 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12249909	Power supply noise reduction by current cancellation circuit	Khaled M. Alashmouny, Zhi Hu	2025-03-11
12160497	Reference clock switching in phase-locked loop circuits	Hairong Yu, Boon-Aik Ang, Yu-Cheng Chen, Litesh Sajnani, Samed Maltabas +5 more	2024-12-03	$369,762,000
11256283	Hybrid asynchronous gray counter with non-gray zone detector for high performance phase-locked loops	Dabin Zhang, Dennis M. Fischette, Jr., Shaobo Liu, Yu-Cheng Chen, Samed Maltabas	2022-02-22	$187,065,000
9979405	Adaptively reconfigurable time-to-digital converter for digital phase-locked loops	Wei Deng, Dennis M. Fischette, Jr., Samed Maltabas	2018-05-22	$72,572,000
9692426	Phase locked loop system with bandwidth measurement and calibration	Boon-Aik Ang, Dennis M. Fischette, Jr.	2017-06-27	$11,625,000
8134417	Automatic amplitude control for voltage controlled oscillator	Dennis M. Fischette, Jr., Alvin Leng Sun Loke, Michael M. Oshima	2012-03-13	$9,355,000
7817761	Test techniques for a delay-locked loop receiver interface	Dwight K. Elvey, Sanjeev K. Maheshwari, Emerson S. Fang	2010-10-19	$4,223,000
7750711	Phase select circuit with reduced hysteresis effect	Sanjeev K. Maheshwari, Emerson S. Fang	2010-07-06	$11,658,000
7545190	Parallel multiplexing duty cycle adjustment circuit with programmable range control	Sanjeev K. Maheshwari, Emerson S. Fang	2009-06-09	$8,157,000
7009548	Variable accuracy pipeline ADC for WLAN communications devices	Boon-Aik Ang	2006-03-07	$15,826,000
6359579	Digital logic correction circuit for a pipeline analog to digital (A/D) converter	—	2002-03-19	$4,163,000
6337651	Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage	—	2002-01-08	$11,293,000
6323800	Pipeline analog to digital (a/d) converter with lengthened hold operation of a first stage	—	2001-11-27	$5,286,000
6295016	Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage	—	2001-09-25	$2,966,000

Meei-Ling Chiang — 14 Patents

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