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Power supply noise reduction by current cancellation circuit |
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Reference clock switching in phase-locked loop circuits |
Hairong Yu, Boon-Aik Ang, Yu-Cheng Chen, Litesh Sajnani, Samed Maltabas +5 more |
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Hybrid asynchronous gray counter with non-gray zone detector for high performance phase-locked loops |
Dabin Zhang, Dennis M. Fischette, Jr., Shaobo Liu, Yu-Cheng Chen, Samed Maltabas |
2022-02-22 |
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Adaptively reconfigurable time-to-digital converter for digital phase-locked loops |
Wei Deng, Dennis M. Fischette, Jr., Samed Maltabas |
2018-05-22 |
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Phase locked loop system with bandwidth measurement and calibration |
Boon-Aik Ang, Dennis M. Fischette, Jr. |
2017-06-27 |
| 8134417 |
Automatic amplitude control for voltage controlled oscillator |
Dennis M. Fischette, Jr., Alvin Leng Sun Loke, Michael M. Oshima |
2012-03-13 |
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Test techniques for a delay-locked loop receiver interface |
Dwight K. Elvey, Sanjeev K. Maheshwari, Emerson S. Fang |
2010-10-19 |
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Phase select circuit with reduced hysteresis effect |
Sanjeev K. Maheshwari, Emerson S. Fang |
2010-07-06 |
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Parallel multiplexing duty cycle adjustment circuit with programmable range control |
Sanjeev K. Maheshwari, Emerson S. Fang |
2009-06-09 |
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Variable accuracy pipeline ADC for WLAN communications devices |
Boon-Aik Ang |
2006-03-07 |
| 6359579 |
Digital logic correction circuit for a pipeline analog to digital (A/D) converter |
— |
2002-03-19 |
| 6337651 |
Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage |
— |
2002-01-08 |
| 6323800 |
Pipeline analog to digital (a/d) converter with lengthened hold operation of a first stage |
— |
2001-11-27 |
| 6295016 |
Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage |
— |
2001-09-25 |
