Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus for a programmable CML to CMOS translator for power/speed adjustment

Apparatus for a programmable CML to CMOS translator for power/speed adjustment

US Patent 5600267 · Granted Feb 4, 1997

Estimated economic value: $6,306,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Low standby power with fast turn on method for non-volatile memory devices2024
Low standby power with fast turn on method for non-volatile memory devices2023
Low standby power with fast turn on method for non-volatile memory devices2021
Low standby power with fast turn on method for non-volatile memory devices2019
Low standby power with fast turn on for non-volatile memory devices2018
Systems, methods, and devices for parallel read and write operations2018
Systems, methods, and devices for parallel read and write operations2017
ESD clamp with a layout-alterable trigger voltage and a holding voltage above th2016
Low standby power with fast turn on for non-volatile memory devices2016
Apparatus for testing a phrase-locked loop in a boundary scan enabled device2010
Field-programmable gate array low voltage differential signaling driver utilizin2009
Apparatus for interfacing and testing a phase locked loop in a field programmabl2008