Patents per Year
Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 10643012 | Concurrent formal verification of logic synthesis | Lisa McIlwain, Michael S. Quayle, Eyal Odiz, Patrick Groeneveld, Kshama Jambhekar +1 more | 2020-05-05 | $63,764,000 |
| 6530072 | Rule based hierarchy generation in a circuit design verification system | Matthew Bellantoni, Richard J. Cloutier | 2003-03-04 | |
| 6219821 | Computers systems and methods for verifying representations of a circuit design | Matthew Bellantoni, Richard Newton, Richard J. Cloutier, Gerard Memmi | 2001-04-17 |