Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Concurrent formal verification of logic synthesis

Concurrent formal verification of logic synthesis

US Patent 10643012 · Granted May 5, 2020

Estimated economic value: $63,764,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Formal gated clock conversion for field programmable gate array (FPGA) synthesis2022
Design-for-testability (DFT) insertion at register-transfer-level (RTL)2019
Optimizing an integrated circuit (IC) design comprising at least one wide-gate o2019
Identifying and using slices in an integrated circuit (IC) design2017
Creating and using a wide-bus data structure to represent a wide-bus in an integ2017
Creating and using a wide-gate data structure to represent a wide-gate in an int2017
Reducing x-pessimism in gate-level simulation and verification2014
Hierarchical verification for equivalence checking of designs2003
Rule based hierarchy generation in a circuit design verification system2003
Method for storing multiple levels of design data in a common database2003
Method of designing a constraint-driven integrated circuit layout2001
Computers systems and methods for verifying representations of a circuit design2001