Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Hierarchical verification for equivalence checking of designs

Hierarchical verification for equivalence checking of designs

US Patent 6668362 · Granted Dec 23, 2003

Estimated economic value: $38,695,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Formal gated clock conversion for field programmable gate array (FPGA) synthesis2022
Concurrent formal verification of logic synthesis2020
Reducing x-pessimism in gate-level simulation and verification2014
System and process of extracting gate-level descriptions from simulation tables 2001