| 10643012 |
Concurrent formal verification of logic synthesis |
Lisa McIlwain, Michael S. Quayle, Patrick Groeneveld, John W. Hagerman, Kshama Jambhekar +1 more |
2020-05-05 |
| 10372858 |
Design-for-testability (DFT) insertion at register-transfer-level (RTL) |
Janet L. Olson, Mukund Sivaraman |
2019-08-06 |
| 10354032 |
Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus |
Jovanka Ciric Vujkovic, Van E. Morgan, Janet L. Olson |
2019-07-16 |
| 9697314 |
Identifying and using slices in an integrated circuit (IC) design |
Jovanka Ciric Vujkovic, Van E. Morgan, Janet L. Olson |
2017-07-04 |
| 9690890 |
Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) design |
Jovanka Ciric Vujkovic, Van E. Morgan, Janet L. Olson |
2017-06-27 |
| 9652573 |
Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) design |
Jovanka Ciric Vujkovic, Van E. Morgan, Janet L. Olson |
2017-05-16 |