Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of designing a constraint-driven integrated circuit layout

Method of designing a constraint-driven integrated circuit layout

US Patent 6230304 · Granted May 8, 2001

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Concurrent formal verification of logic synthesis2020
Timing closure methodology including placement with initial delay values2017
Timing closure methodology including placement with initial delay values2013
Representing the design of a sub-module in a hierarchical integrated circuit des2006
Method for generating design constraints for modules in a hierarchical integrate2005
Timing closure methodology2004
Timing optimization in presence of interconnect delays2003
Method for storing multiple levels of design data in a common database2003
Method for storing multiple levels of design data in a common database2003
Automated design of parallel drive standard cells2002
Timing closure methodology2002
Method for the physical placement of an integrated circuit adaptive to netlist c2002