Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10599800 | Formal clock network analysis, visualization, verification and generation | Mohamed Shaker Sarwary, Hans-Joerg Peter, Guillaume Plassan, Mohammad H. Movahed-Ezazi | 2020-03-24 |
| 9721058 | System and method for reactive initialization based formal verification of electronic logic design | Mohamed Shaker Sarwary, Hans-Jorg Peter, Fahim Rahim, Mohammad H. Movahed-Ezazi | 2017-08-01 |
| 9201992 | Method and apparatus using formal methods for checking generated-clock timing definitions | Sridhar Gangadharan, Manish Goel, Mohammad H. Movahed-Ezazi | 2015-12-01 |
| 8656328 | System and method for abstraction of a circuit portion of an integrated circuit | Mohamed Shaker Sarwary, Mohammed Movahed-Ezazi, Manish Gupta, Chandan Kumar | 2014-02-18 |