Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9201992 | Method and apparatus using formal methods for checking generated-clock timing definitions | Barsneya Chakrabarti, Manish Goel, Mohammad H. Movahed-Ezazi | 2015-12-01 |
| 8788993 | Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design | Mohammad H. Movahed-Ezazi, Shaker Sarwary, Fadi Maamari, Subir Chandra Ray | 2014-07-22 |
| 8775989 | Computer-aided design system and methods thereof for merging design constraint files across operational modes | Manish Goel, Amit Handa | 2014-07-08 |
| 8533647 | Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design | Mohammad H. Movahed-Ezazi, Shaker Sarwary, Fadi Maamari, Subir Ray | 2013-09-10 |
| 7882483 | Method for checking constraints equivalence of an integrated circuit design | Manish Goel, Pratyush K. Prasoon, Suraj Bharech | 2011-02-01 |