Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7536662 | Method for recognizing and verifying FIFO structures in integrated circuit designs | Shaker Sarwary, Jun Yuan, Ashish Hari, Paras Mal Jain | 2009-05-19 |
| 7506292 | Method for clock synchronization validation in integrated circuit design | Mohamed Shaker Sarwary, Mohammad Movahed Ezazi | 2009-03-17 |
| 7421670 | Chip development system enabled for the handling of multi-level circuit design data | — | 2008-09-02 |
| 7216321 | Pattern recognition in an integrated circuit design | Pratyush Kumar Prasoon, Manish Bhatia | 2007-05-08 |
| 7073146 | Method for clock synchronization validation in integrated circuit design | Mohamed Shaker Sarwary, Mohammad Movahed Ezazi | 2006-07-04 |
| 6993733 | Apparatus and method for handling of multi-level circuit design data | — | 2006-01-31 |
| D314925 | Circuit tester | — | 1991-02-26 |
| 4880306 | Method of checking collinearity | — | 1989-11-14 |
| 4505349 | Steering means for, and in combination with, an articulated _vehicle | — | 1985-03-19 |