Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11238202 | Verifying glitches in reset path using formal verification and simulation | Sudeep Mondal, Anshul Tuteja | 2022-02-01 |
| 9721057 | System and method for netlist clock domain crossing verification | Malay Ganai, Mohamed Shaker Sarwary, Maher Mneimneh, Mohammad H. Movahed-Ezazi, Pronay Kumar Biswas +1 more | 2017-08-01 |
| 7536662 | Method for recognizing and verifying FIFO structures in integrated circuit designs | Shaker Sarwary, Jun Yuan, Bernard Murphy, Ashish Hari | 2009-05-19 |