XD

Xiaoqun Du

CS Cadence Design Systems: 8 patents #167 of 2,263Top 8%
📍 New Providence, NJ: #133 of 512 inventorsTop 30%
🗺 New Jersey: #11,005 of 69,400 inventorsTop 20%
Overall (All Time): #652,002 of 4,157,543Top 20%
8
Patents All Time

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
8418101 Temporal decomposition for design and verification Andreas Kuehlmann 2013-04-09
8413090 Temporal decomposition for design and verification Andreas Kuehlmann 2013-04-02
7900173 Temporal decomposition for design and verification Andreas Kuehlmann 2011-03-01
7712059 Coverage metric and coverage computation for verification based on design partitions Robert P. Kurshan, Kavita Ravi 2010-05-04
7596770 Temporal decomposition for design and verification Andreas Kuehlmann 2009-09-29
7444274 Method and system for verifying circuit designs through propagation of assertions Manu Chopra, Alok Jain, Robert P. Kurshan, Franz Erich Marschner, Kavita Ravi 2008-10-28
7181708 Coverage metric and coverage computation for verification based on design partitions Robert P. Kurshan, Kavita Ravi 2007-02-20
7047510 Method and system for partitioning an integrated circuit design Manu Chopra, Ronald H. Hardin, Alok Jain, Robert P. Kurshan, Pratik Mahajan +2 more 2006-05-16