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Jesse Peter Surprise

IBM: 14 patents #8,004 of 70,183Top 15%
Overall (All Time): #335,360 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12367331 Approach to child block pinning Eduard Herkel, Ofer Geva, Faisal Hasan 2025-07-22
11797740 Even apportionment based on positive timing slack threshold Eduard Herkel, Ofer Geva, Michael H. Wood, Chris Aaron Cavitt, Tsz-Mei Ko 2023-10-24
11775730 Hierarchical large block synthesis (HLBS) filling Ofer Geva, Brittany Duffy, Timothy A. Schell, Eduard Herkel 2023-10-03
11720732 Determining a blended timing constraint that satisfies multiple timing constraints and user-selected specifications Chris Aaron Cavitt, Brandon Albert Bruen, Eric A. Foreman 2023-08-08
10943051 Metal fill shape removal from selected nets Gerald Strevig, III, Shawn Kollesar, Chris Aaron Cavitt, Chaobo Li, Dina Hamid +1 more 2021-03-09
10943040 Clock gating latch placement Gerald Strevig, III, Shawn Kollesar, Adam P. Matheny 2021-03-09
10902175 Cross-hierarchical block pin placement Gerald Strevig, III, Shawn Kollesar 2021-01-26
10902178 Wire orientation-based latch shuddling Gerald Strevig, III, Shawn Kollesar 2021-01-26
10831967 Local clock buffer controller placement and connectivity Gerald Strevig, III, Shawn Kollesar, Michael A. Kazda 2020-11-10
10719654 Placement and timing aware wire tagging Manuel Beck, Florian Braun, Lukas Dällenbach, Heinz Josef Hemmes, Marvin von der Ehe 2020-07-21
10042972 Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design Alexandra Echegaray, Bernd Kemmier, Stephen Szulewski 2018-08-07
9934341 Simulation of modifications to microprocessor design Christopher J. Berry, Chris Aaron Cavitt, Adam P. Matheny, Jose L. Neves, Michael H. Wood 2018-04-03
9928322 Simulation of modifications to microprocessor design Christopher J. Berry, Chris Aaron Cavitt, Adam P. Matheny, Jose L. Neves, Michael H. Wood 2018-03-27
9684756 Assigning nets to wiring planes using zero wire load and signal propagation timing for chip design Alexandra Echegaray, Bernd Kemmler, Stephen Szulewski 2017-06-20