Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11055461 | Designing semiconductor circuit test elements | Manuel Beck | 2021-07-06 |
| 10719654 | Placement and timing aware wire tagging | Manuel Beck, Florian Braun, Lukas Dällenbach, Heinz Josef Hemmes, Jesse Peter Surprise | 2020-07-21 |
| 10572618 | Enabling automatic staging for nets or net groups with VHDL attributes | Manuel Beck, Florian Braun, Lukas Dällenbach, Heinz Josef Hemmes | 2020-02-25 |