Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11983477 | Routing layer re-optimization in physical synthesis | Lakshmi N. Reddy, Ying Zhou, Alexander J. Suess | 2024-05-14 |
| 10706194 | Boundary assertion-based power recovery in integrated circuit design | Alexander J. Suess | 2020-07-07 |
| 10671791 | Dynamic microprocessor gate design tool for area/timing margin control | Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Nancy Y. Zhou | 2020-06-02 |
| 10216882 | Critical path straightening system based on free-space aware and timing driven incremental placement | Jinwook Jung, Frank J. Musante, Gi-Joon Nam, Shyam Ramji, Lakshmi N. Reddy +1 more | 2019-02-26 |
| 10078722 | Dynamic microprocessor gate design tool for area/timing margin control | Michael A. Kazda, Arjen A. Mets, Lakshmi N. Reddy, Nancy Y. Zhou | 2018-09-18 |
| 7325210 | Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect | Vasant Rao, Jun Zhou, Jeffrey P. Soreff, Patrick M. Williams, David J. Hathaway | 2008-01-29 |
| 7093208 | Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices | Patrick M. Williams, Ee K. Cho, David J. Hathaway, Mei-Ting Hsu, Lawrence K. Lange +3 more | 2006-08-15 |