Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10839133 | Circuit layout similarity metric for semiconductor testsite coverage | Rasit Onur Topaloglu, Dureseti Chidambarrao, Werner Rausch | 2020-11-17 |
| 8473885 | Physical design system and method | John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin +6 more | 2013-06-25 |
| 8219943 | Physical design system and method | John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin +6 more | 2012-07-10 |
| 7536664 | Physical design system and method | John M. Cohn, James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin +6 more | 2009-05-19 |
| 7178120 | Method for performing timing closure on VLSI chips in a distributed environment | Nathaniel D. Hieter, David J. Hathaway, Prabhakar Kudva, David S. Kung | 2007-02-13 |
| 7047163 | Method and apparatus for applying fine-grained transforms during placement synthesis interaction | Kanad Chakraborty, Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy, Andrew J. Sullivan +1 more | 2006-05-16 |
| 6966046 | CMOS tapered gate and synthesis method | Brian W. Curran, Lisa Bryant Lacey, Gregory A. Northrop, Ruchir Puri | 2005-11-15 |
| 6557159 | Method for preserving regularity during logic synthesis | Thomas Kutzschebauch | 2003-04-29 |
| 6334205 | Wavefront technology mapping | Mahesh A. Iyer, Andrew J. Sullivan | 2001-12-25 |
| 6167557 | Method and apparatus for logic synthesis employing size independent timing optimization | Prabhakarn N. Kudva, David S. Kung | 2000-12-26 |