RL

Ravichander Ledalla

IBM: 7 patents #14,640 of 70,183Top 25%
Overall (All Time): #723,280 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10169526 Incremental parasitic extraction for coupled timing and power optimization Kerim Kalafala, Tsz-Mei Ko, Alice H. Lee, Adam P. Matheny, Jose L. Neves +1 more 2019-01-01
9858383 Incremental parasitic extraction for coupled timing and power optimization Kerim Kalafala, Tsz-Mei Ko, Alice H. Lee, Adam P. Matheny, Jose L. Neves +1 more 2018-01-02
9607124 Method of hierarchical timing closure employing dynamic load-sensitive feedback constraints Adil Bhanji, Kerim Kalafala, Debjit Sinha, Chandramouli Visweswariah, Michael H. Wood 2017-03-28
9342639 Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions Christine T. Casey, Kerim Kalafala, Debjit Sinha 2016-05-17
8201120 Timing point selection for a static timing analysis in the presence of interconnect electrical elements Jeffrey P. Soreff, Barry Lee Dorfman, Jeffrey G. Hemmett, Vasant Rao, Fred Yang 2012-06-12
7870515 System and method for improved hierarchical analysis of electronic circuits Philip G. Shephard, III, Vasant Rao, Jeffrey P. Soreff 2011-01-11
6763504 Method for reducing RC parasitics in interconnect networks of an integrated circuit Vasant Rao, Jeffrey P. Soreff, Fred Yang 2004-07-13