SW

Steven E. Washburn

IBM: 8 patents #13,150 of 70,183Top 20%
Overall (All Time): #630,192 of 4,157,543Top 20%
8
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11017137 Efficient projection based adjustment evaluation in static timing analysis of integrated circuits Chaitanya Ravindra Peddawad, Jeffrey G. Hemmett, Jason D. Morsey, Peter C. Elmendorf, Debjit Sinha +1 more 2021-05-25
10565336 Pessimism reduction in cross-talk noise determination used in integrated circuit design Jason D. Morsey, Patrick M. Williams, James D. Warnock 2020-02-18
10552570 Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values Tsz-Mei Ko, Thomas G. Mitchell, Jason D. Morsey, Patrick M. Williams 2020-02-04
10254784 Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entities Jason D. Morsey, Patrick M. Williams, Michael H. Wood 2019-04-09
10248753 Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values Tsz-Mei Ko, Thomas G. Mitchell, Jason D. Morsey, Patrick M. Williams 2019-04-02
10169514 Approximation of resistor-capacitor circuit extraction for thread-safe design changes Tsz-Mei Ko, Jason D. Morsey, Patrick M. Williams 2019-01-01
6848089 Method and apparatus for detecting devices that can latchup Micah Galland, Peter A. Habitz 2005-01-25
6571374 Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips Stephen L. Runyon, Robert T. Sayah, Joseph Roland Verock 2003-05-27