DS

Debjit Sinha

IBM: 36 patents #2,696 of 70,183Top 4%
📍 Wappingers Falls, NY: #49 of 884 inventorsTop 6%
🗺 New York: #3,082 of 115,490 inventorsTop 3%
Overall (All Time): #93,946 of 4,157,543Top 3%
36
Patents All Time

Issued Patents All Time

Showing 26–36 of 36 patents

Patent #TitleCo-InventorsDate
8589842 Device-based random variability modeling in timing analysis Manjul Bhushan, Eric Jason Fluhr, Stephen G. Shuma, Chandramouli Visweswariah, James D. Warnock +1 more 2013-11-19
8560989 Statistical clock cycle computation Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, James C. Gregerson +6 more 2013-10-15
8458632 Efficient slack projection for truncated distributions Eric A. Foreman, James C. Gregerson, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran +3 more 2013-06-04
8418107 Performing statistical timing analysis with non-separable statistical and deterministic variations Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov 2013-04-09
8141025 Method of performing timing analysis on integrated circuit chips with consideration of process variations Eric A. Foreman, Peter A. Habitz, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov 2012-03-20
8122411 Method of performing static timing analysis considering abstracted cell's interconnect parasitics Soroush Abbaspour 2012-02-21
8122404 Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits Adil Bhanji, Barry Lee Dorfman, Kerim Kalafala, Natesan Venkateswaran, Chandramouli Visweswariah 2012-02-21
8103997 Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits Soroush Abbaspour, Adil Bhanji, Jeffrey M. Ritzinger 2012-01-24
8104005 Method and apparatus for efficient incremental statistical timing analysis and optimization Natesan Venkateswaran, Chandramouli Visweswariah, Jinjun Xiong, Vladimir Zolotov 2012-01-24
7788617 Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis Adil Bhanji, Soroush Abbaspour, Peter Feldmann 2010-08-31
7685549 Method of constrained aggressor set selection for crosstalk induced noise Soroush Abbaspour, Ayesha Akhter, Gregory M. Schaeffer, David J. Widiger 2010-03-23