Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8185371 | Modeling full and half cycle clock variability | Adil Bhanji, Sean Michael Carey, Jack DiLullo, Prashant D Joshi, Don Richard Rozales +1 more | 2012-05-22 |
| 8103989 | Method and system for changing circuits in an integrated circuit | Nathan A. Dotson, Jonathan Y. Chen, David L. Rude | 2012-01-24 |
| 7882472 | Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process | Nicholas P. Sardino, Sean Michael Carey, Christopher M. Carney | 2011-02-01 |
| 7752585 | Method, apparatus, and computer program product for stale NDR detection | Christopher M. Carney | 2010-07-06 |
| 7480886 | VLSI timing optimization with interleaved buffer insertion and wire sizing stages | Christopher M. Carney | 2009-01-20 |