| D1065212 |
Display device screen with graphical user interface |
Erica Jean Virtue, Kyle McDowell, Russell Hampton |
2025-03-04 |
| 7895539 |
System for improving a logic circuit and associated methods |
Jose L. Neves, Biagio Pluchino |
2011-02-22 |
| 7882472 |
Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process |
Nicholas P. Sardino, Sean Michael Carey, Vern A. Victoria |
2011-02-01 |
| 7809874 |
Method for resource sharing in a multiple pipeline environment |
Patrick J. Meaney, Michael Fee |
2010-10-05 |
| 7752585 |
Method, apparatus, and computer program product for stale NDR detection |
Vern A. Victoria |
2010-07-06 |
| 7480886 |
VLSI timing optimization with interleaved buffer insertion and wire sizing stages |
Vern A. Victoria |
2009-01-20 |
| 7469399 |
Semi-flattened pin optimization process for hierarchical physical designs |
Christopher J. Berry, David L. Rude, Eddy St. Juste |
2008-12-23 |
