Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6832277 | Method and apparatus for transmitting data that utilizes delay elements to reduce capacitive coupling | Christopher McCall Durham | 2004-12-14 |
| 6735754 | Method and apparatus to facilitate global routing for an integrated circuit layout | Sharad Mehrotra | 2004-05-11 |
| 6694502 | Data structure for fine-grid multi-level VLSI routing and method for storing the data structure in a computer readable medium | Sharad Mehrotra | 2004-02-17 |
| 6601222 | Coupled noise estimation and avoidance of noise-failure using global routing information | Sharad Mehrotra, David J. Widiger | 2003-07-29 |
| 6467069 | Timing closure and noise avoidance in detailed routing | Sharad Mehrotra | 2002-10-15 |
| 6415422 | Method and system for performing capacitance estimations on an integrated circuit design routed by a global routing tool | Sharad Mehrotra | 2002-07-02 |
| 6360350 | Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms | Carol Ivash Gabele, Stephen T. Quay, Paul G. Villarrubia, Jean-Paul Watson | 2002-03-19 |
| 6230302 | Method and system for performing timing analysis on an integrated circuit design | Carol Ivash Gabele, Stephen T. Quay, Paul G. Villarrubia, Alexander K. Spencer | 2001-05-08 |
| 6218631 | Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk | Asmus Hetzel, Erich Klink, Juergen Koehl, Dieter Wendel | 2001-04-17 |
| 5831870 | Method and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimation | Alan Folta, Sharad Mehrotra, Paul G. Villarrubia | 1998-11-03 |
| 5764532 | Automated method and system for designing an optimized integrated circuit | — | 1998-06-09 |
| 5649170 | Interconnect and driver optimization for high performance processors | Barbara A. Chappell, Phoung Kim Phan, George Anthony Sai Halasz | 1997-07-15 |
| 5045913 | Bit stack compatible input/output circuits | Robert P. Masleid | 1991-09-03 |
| 4988636 | Method of making bit stack compatible input/output circuits | Robert P. Masleid | 1991-01-29 |
| 4446611 | Method of making a saturation-limited bipolar transistor device | David L. Bergeron | 1984-05-08 |
| 4390890 | Saturation-limited bipolar transistor device | David L. Bergeron | 1983-06-28 |
| 4363110 | Non-volatile dynamic RAM cell | Howard L. Kalter, Harish N. Kotecha | 1982-12-07 |