Issued Patents All Time
Showing 26–27 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6086238 | Method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation | Sharad Mehrotra, Paul G. Villarrubia | 2000-07-11 |
| 6005416 | Compiled self-resetting CMOS logic array macros | Michael P. Beakes, Barbara Alana Chappell, Terry I. Chappell, Gary S. Ditlow, Barry Lee Dorfman +2 more | 1999-12-21 |