Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10366196 | Standard cell architecture for diffusion based on fin count | Anthony Correale, Jr., Tracey Della Rova, William Goodall, III | 2019-07-30 |
| 10282503 | Mitigating length-of-diffusion effect for logic cells and placement thereof | Anthony Correale, Jr., Tracey Della Rova | 2019-05-07 |
| 10236302 | Standard cell architecture for diffusion based on fin count | Anthony Correale, Jr., Tracey Della Rova, William Goodall, III | 2019-03-19 |
| 9852080 | Efficiently generating selection masks for row selections within indexed address spaces | David Paul Hoff, Milind Ram Kulkarni | 2017-12-26 |
| 9558308 | Compiler for closed-loop 1×N VLSI design | Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid, Paul M. Steinmetz | 2017-01-31 |
| 9306570 | Continuous diffusion configurable standard cell architecture | Satyanarayana Sahu, Joshua Puckett, Ohsang Kwon, William Goodall, III | 2016-04-05 |
| 9070551 | Method and apparatus for a diffusion bridged cell library | James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki, Chock Hing Gan +3 more | 2015-06-30 |
| 8887113 | Compiler for closed-loop 1xN VLSI design | Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid, Paul M. Steinmetz | 2014-11-11 |
| 8782576 | Method and apparatus for a diffusion bridged cell library | James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki, Chock Hing Gan +3 more | 2014-07-15 |
| 8739086 | Compiler for closed-loop 1×N VLSI design | Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid, Paul M. Steinmetz | 2014-05-27 |
| 8516428 | Methods, systems, and media to improve manufacturability of semiconductor devices | Anthony Correale, Jr. | 2013-08-20 |
| 8298888 | Creating integrated circuit capacitance from gate array structures | Anthony Correale, Jr., Douglass T. Lamb, Nishith Rohatgi | 2012-10-30 |
| 8188516 | Creating integrated circuit capacitance from gate array structures | Anthony Correale, Jr., Douglass T. Lamb, Nishith Rohatgi | 2012-05-29 |
| 8156458 | Uniquification and parent-child constructs for 1xN VLSI design | Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid, Paul M. Steinmetz | 2012-04-10 |
| 8141016 | Integrated design for manufacturing for 1×N VLSI design | Anthony Correale, Jr., Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2012-03-20 |
| 8136062 | Hierarchy reassembler for 1×N VLSI design | Paul M. Steinmetz, Anthony Correale, Jr., Irfan Rashid, Matthew W. Baker | 2012-03-13 |
| 8132134 | Closed-loop 1×N VLSI design system | Anthony Correale, Jr., Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2012-03-06 |
| 8122399 | Compiler for closed-loop 1×N VLSI design | Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid, Paul M. Steinmetz | 2012-02-21 |
| 7966598 | Top level hierarchy wiring via 1×N compiler | Anthony L. Polomik, Anthony Correale, Jr., Matthew W. Baker, Irfan Rashid, Paul M. Steinmetz | 2011-06-21 |
| 7908571 | Systems and media to improve manufacturability of semiconductor devices | Anthony Correale, Jr. | 2011-03-15 |
| 7904847 | CMOS circuit leakage current calculator | Anthony Correale, Jr., Nishith Rohatgi | 2011-03-08 |
| 7882385 | Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank | Nicole M. Arnold, Matthew W. Baker, Anthony Correale, Jr., Paul M. Steinmetz | 2011-02-01 |
| 7728362 | Creating integrated circuit capacitance from gate array structures | Anthony Correale, Jr., Douglass T. Lamb, Nishith Rohatgi | 2010-06-01 |
| 7672188 | System for blocking multiple memory read port activation | Anthony Correale, Jr., Matthew W. Baker, Michael B. Mitchell, Nishith Rohatgi | 2010-03-02 |
| 7343570 | Methods, systems, and media to improve manufacturability of semiconductor devices | Anthony Correale, Jr. | 2008-03-11 |