| 10541044 |
Providing efficient handling of memory array failures in processor-based systems |
Thomas Philip Speier, Viren Ramesh Patel, Michael ThaiThanh Phan, Manish Garg, Kevin N. Magill +2 more |
2020-01-21 |
| 9558308 |
Compiler for closed-loop 1×N VLSI design |
Benjamin J. Bowers, Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid |
2017-01-31 |
| 9201801 |
Computing device with asynchronous auxiliary execution unit |
Bechara F. Boury, Michael B. Mitchell, Kenichi Tsuchiya |
2015-12-01 |
| 8887113 |
Compiler for closed-loop 1xN VLSI design |
Benjamin J. Bowers, Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid |
2014-11-11 |
| 8739086 |
Compiler for closed-loop 1×N VLSI design |
Benjamin J. Bowers, Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid |
2014-05-27 |
| 8156458 |
Uniquification and parent-child constructs for 1xN VLSI design |
Matthew W. Baker, Benjamin J. Bowers, Anthony Correale, Jr., Irfan Rashid |
2012-04-10 |
| 8141016 |
Integrated design for manufacturing for 1×N VLSI design |
Anthony Correale, Jr., Benjamin J. Bowers, Matthew W. Baker, Irfan Rashid |
2012-03-20 |
| 8136062 |
Hierarchy reassembler for 1×N VLSI design |
Benjamin J. Bowers, Anthony Correale, Jr., Irfan Rashid, Matthew W. Baker |
2012-03-13 |
| 8132134 |
Closed-loop 1×N VLSI design system |
Anthony Correale, Jr., Matthew W. Baker, Benjamin J. Bowers, Irfan Rashid |
2012-03-06 |
| 8122399 |
Compiler for closed-loop 1×N VLSI design |
Benjamin J. Bowers, Matthew W. Baker, Anthony Correale, Jr., Irfan Rashid |
2012-02-21 |
| 7966598 |
Top level hierarchy wiring via 1×N compiler |
Anthony L. Polomik, Benjamin J. Bowers, Anthony Correale, Jr., Matthew W. Baker, Irfan Rashid |
2011-06-21 |
| 7882385 |
Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank |
Nicole M. Arnold, Matthew W. Baker, Benjamin J. Bowers, Anthony Correale, Jr. |
2011-02-01 |
| 7752396 |
Promoting a line from shared to exclusive in a cache |
James Norris Dieffenderfer, Praveen Karandikar, Michael B. Mitchell, Thomas Philip Speier |
2010-07-06 |
| 7523265 |
Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache |
James Norris Dieffenderfer, Praveen Karandikar, Michael B. Mitchell, Thomas Philip Speier |
2009-04-21 |
| 7319578 |
Digital power monitor and adaptive self-tuning power management |
James Norris Dieffenderfer, Praveen Karandikar, Michael B. Mitchell, Thomas Philip Speier |
2008-01-15 |
