BB

Bechara F. Boury

IBM: 18 patents #6,125 of 70,183Top 9%
IN Intel: 1 patents #18,218 of 30,777Top 60%
Overall (All Time): #257,593 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9201801 Computing device with asynchronous auxiliary execution unit Michael B. Mitchell, Paul M. Steinmetz, Kenichi Tsuchiya 2015-12-01
5966728 Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device Nader Amini, Sherwood Brannon, Richard Louis Horne 1999-10-12
5835738 Address space architecture for multiple bus computer systems John W. Blackledge, Jr., Bradly G. Frey, James Dalgleish Reid, Ronald Valli 1998-11-10
5673414 Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device Nader Amini, Sherwood Brannon, Richard Louis Horne 1997-09-30
5644729 Bidirectional data buffer for a bus-to-bus interface unit in a computer system Nader Amini, Sherwood Brannon, Richard Louis Horne, Terence J. Lohman 1997-07-01
5621897 Method and apparatus for arbitrating for a bus to enable split transaction bus protocols Charles Edward Kuhlmann, Terence J. Lohman, Neil W. Songer, Ronald Valli 1997-04-15
5619729 Power management of DMA slaves with DMA traps Patrick M. Bland, Richard Gerard Hofmann, Robert T. Jackson, Nader Amini, Jayesh M. Joshi 1997-04-08
5548786 Dynamic bus sizing of DMA transfers Nader Amini, Sherwood Brannon, Ian A. Concilio, Richard Gerard Hofmann, Terence J. Lohman 1996-08-20
5544346 System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus Nader Amini, Sherwood Brannon, Richard Louis Horne, Terence J. Lohman 1996-08-06
5499346 Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus Nader Amini, Patrick M. Bland, Robert T. Jackson 1996-03-12
5450551 System direct memory access (DMA) support logic for PCI based computer system Nader Amini, Patrick M. Bland, Richard Gerard Hofmann, Terence J. Lohman 1995-09-12
5396602 Arbitration logic for multiple bus computer system Nader Amini, Patrick M. Bland, Richard Gerard Hofmann, Terence J. Lohman 1995-03-07
5381538 DMA controller including a FIFO register and a residual register for data buffering and having different operating modes Nader Amini, Terence J. Lohman 1995-01-10
5333274 Error detection and recovery in a DMA controller Nader Amini, Sherwood Brannon, Richard Gerard Hofmann, Terence J. Lohman 1994-07-26
5313627 Parity error detection and recovery Nader Amini, Sherwood Brannon, Richard Louis Horne 1994-05-17
5301282 Controlling bus allocation using arbitration hold Nader Amini, Terence J. Lohman 1994-04-05
5265211 Arbitration control logic for computer system having dual bus architecture Nader Amini, Richard Louis Horne, Terence J. Lohman 1993-11-23
5239631 CPU bus allocation control Terence J. Lohman, Long D. Nguyen 1993-08-24