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Nader Amini

IBM: 23 patents #4,681 of 70,183Top 7%
IN Intel: 1 patents #18,218 of 30,777Top 60%
Overall (All Time): #186,895 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
5966728 Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device Bechara F. Boury, Sherwood Brannon, Richard Louis Horne 1999-10-12
5761533 Computer system with varied data transfer speeds between system components and memory Alfredo Aldereguia, Daryl Cromer, Richard Louis Horne, Ashu Kohli, Kimberly K. Sendlein +1 more 1998-06-02
5673414 Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device Bechara F. Boury, Sherwood Brannon, Richard Louis Horne 1997-09-30
5659696 Method and apparatus for determining address location and taking one of two actions depending on the type of read/write data transfer required Richard Louis Horne 1997-08-19
5644729 Bidirectional data buffer for a bus-to-bus interface unit in a computer system Bechara F. Boury, Sherwood Brannon, Richard Louis Horne, Terence J. Lohman 1997-07-01
5619729 Power management of DMA slaves with DMA traps Patrick M. Bland, Richard Gerard Hofmann, Robert T. Jackson, Bechara F. Boury, Jayesh M. Joshi 1997-04-08
5581714 Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus) Ashu Kohli, Gregory N. Santos 1996-12-03
5564026 Bus-to-bus pacing logic for improving information transfers in a multi-bus information handling system Ashu Kohli, Gregory N. Santos 1996-10-08
5551009 Expandable high performance FIFO design which includes memory cells having respective cell multiplexors Bechara E. Boury, Sherwood Brannon, Terence J. Lohman 1996-08-27
5548786 Dynamic bus sizing of DMA transfers Bechara F. Boury, Sherwood Brannon, Ian A. Concilio, Richard Gerard Hofmann, Terence J. Lohman 1996-08-20
5544346 System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus Bechara F. Boury, Sherwood Brannon, Richard Louis Horne, Terence J. Lohman 1996-08-06
5542055 System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices Kazushi Yamauchi 1996-07-30
5522050 Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus Ashu Kohli, Gregory N. Santos 1996-05-28
5499346 Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus Patrick M. Bland, Bechara F. Boury, Robert T. Jackson 1996-03-12
5450551 System direct memory access (DMA) support logic for PCI based computer system Patrick M. Bland, Bechara F. Boury, Richard Gerard Hofmann, Terence J. Lohman 1995-09-12
5448703 Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus Ashu Kohli 1995-09-05
5396602 Arbitration logic for multiple bus computer system Patrick M. Bland, Bechara F. Boury, Richard Gerard Hofmann, Terence J. Lohman 1995-03-07
5381538 DMA controller including a FIFO register and a residual register for data buffering and having different operating modes Bechara F. Boury, Terence J. Lohman 1995-01-10
5333274 Error detection and recovery in a DMA controller Bechara F. Boury, Sherwood Brannon, Richard Gerard Hofmann, Terence J. Lohman 1994-07-26
5313627 Parity error detection and recovery Bechara F. Boury, Sherwood Brannon, Richard Louis Horne 1994-05-17
5301282 Controlling bus allocation using arbitration hold Bechara F. Boury, Terence J. Lohman 1994-04-05
5265211 Arbitration control logic for computer system having dual bus architecture Bechara F. Boury, Richard Louis Horne, Terence J. Lohman 1993-11-23
5255374 Bus interface logic for computer system having dual bus architecture Alfredo Aldereguia, Richard Louis Horne, Terence J. Lohman, Cang Ngoc Tran 1993-10-19