GS

Gregory N. Santos

CC Compaq Computer: 14 patents #43 of 1,604Top 3%
IBM: 4 patents #21,733 of 70,183Top 35%
HP HP: 2 patents #5,870 of 16,619Top 40%
Apple: 1 patents #12,251 of 18,612Top 70%
Overall (All Time): #205,056 of 4,157,543Top 5%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12160497 Reference clock switching in phase-locked loop circuits Hairong Yu, Boon-Aik Ang, Yu-Cheng Chen, Litesh Sajnani, Samed Maltabas +5 more 2024-12-03
6990546 Hot docking drive wedge and port replicator Jeffrey Tang, Ronald P. Meyers, Jr. 2006-01-24
6665765 Hot docking drive wedge and port replicator Jeffrey Tang, Ronald P. Meyers, Jr. 2003-12-16
6078338 Accelerated graphics port programmable memory access arbiter Ronald T. Horan, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo 2000-06-20
6040845 Device and method for reducing power consumption within an accelerated graphics port target Maria L. Melo 2000-03-21
5999743 System and method for dynamically allocating accelerated graphics port memory space Ronald T. Horan, Phillip M. Jones, Robert A. Lester, Robert C. Elliot 1999-12-07
5999198 Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device Ronald T. Horan, Phillip M. Jones, Robert A. Lester, Robert C. Elliott 1999-12-07
5990914 Generating an error signal when accessing an invalid memory page Ronald T. Horan, Phillip M. Jones, Robert A. Lester, Robert C. Elliott 1999-11-23
5986677 Accelerated graphics port read transaction merging Phillip M. Jones, Ronald T. Horan 1999-11-16
5949436 Accelerated graphics port multiple entry gart cache allocation system and method Ronald T. Horan, Phillip M. Jones, Robert A. Lester, Jerome J. Johnson, Michael J. Collins 1999-09-07
5936640 Accelerated graphics port memory mapped status and control registers Ronald T. Horan, Phillip M. Jones, Robert A. Lester, Robert C. Elliott 1999-08-10
5933158 Use of a link bit to fetch entries of a graphic address remapping table Robert C. Elliott 1999-08-03
5914730 System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests Robert C. Elliott 1999-06-22
5914727 Valid flag for disabling allocation of accelerated graphics port memory space Ronald T. Horan, Phillip M. Jones, Robert A. Lester, Robert C. Elliott 1999-06-22
5864688 Apparatus and method for positively and subtractively decoding addresses on a bus David J. Maguire, Dwight D. Riley, James R. Edwards 1999-01-26
5781748 Computer system utilizing two ISA busses coupled to a mezzanine bus David J. Maguire, Dwight D. Riley, James R. Edwards 1998-07-14
5761460 Reconfigurable dual master IDE interface David J. Maguire, William C. Hallowell, James R. Edwards 1998-06-02
5581714 Bus-to-bus read prefetch logic for improving information transfers in a multi-bus information handling system (bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus) Nader Amini, Ashu Kohli 1996-12-03
5564026 Bus-to-bus pacing logic for improving information transfers in a multi-bus information handling system Nader Amini, Ashu Kohli 1996-10-08
5550989 Bridge circuit that can eliminate invalid data during information transfer between buses of different bitwidths — 1996-08-27
5522050 Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus Nader Amini, Ashu Kohli 1996-05-28