| 6279087 |
System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations |
Khaldoun Alzien, Robert C. Elliott, David J. Maguire |
2001-08-21 |
| 6241400 |
Configuration logic within a PCI compliant bus interface unit which can be selectively disconnected from a clocking source to conserve power |
Khaldoun Alzien |
2001-06-05 |
| 6243817 |
Device and method for dynamically reducing power consumption within input buffers of a bus interface unit |
James R. Reif, David J. Maguire |
2001-06-05 |
| 6212590 |
Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base |
Todd Deschepper, Jeffrey Wilson |
2001-04-03 |
| 6199131 |
Computer system employing optimized delayed transaction arbitration technique |
Khaldoun Alzien, Todd Deschepper |
2001-03-06 |
| 6154838 |
Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events |
Hung Q. Le, David J. DeLisle |
2000-11-28 |
| 6040845 |
Device and method for reducing power consumption within an accelerated graphics port target |
Gregory N. Santos |
2000-03-21 |
| 5991833 |
Computer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions |
Shaun Wandler, Todd Deschepper |
1999-11-23 |
| 5987555 |
Dynamic delayed transaction discard counter in a bus bridge of a computer system |
Khaldoun Alzien, Todd Deschepper |
1999-11-16 |
| 5923859 |
Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus |
Robert A. Lester |
1999-07-13 |
| 5918026 |
PCI to PCI bridge for transparently completing transactions between agents on opposite sides of the bridge |
Khaldoun Alzien |
1999-06-29 |
| 5867728 |
Preventing corruption in a multiple processor computer system during a peripheral device configuration cycle |
James R. Reif |
1999-02-02 |
| 5819087 |
Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events |
Hung Q. Le, David J. DeLisle |
1998-10-06 |
| 5797020 |
Bus master arbitration circuitry having improved prioritization |
Randy M. Bonella |
1998-08-18 |
| 5790869 |
Circuit for selectively preventing a microprocessor from posting write cycles |
Brian B. Tucker, Randy M. Bonella |
1998-08-04 |
| 5625824 |
Circuit for selectively preventing a microprocessor from posting write cycles |
Brian B. Tucker, Randy M. Bonella |
1997-04-29 |
| 5553248 |
System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal |
Jeff W. Wolford, Michael Moriarty, Paul R. Culley, Arnold Thomas Schnell |
1996-09-03 |
| 5553310 |
Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems |
Mark Taylor, Paul R. Culley, Roger E. Tipley |
1996-09-03 |
| 5471590 |
Bus master arbitration circuitry having improved prioritization |
Randy M. Bonella |
1995-11-28 |
| 5138706 |
Password protected enhancement configuration register for addressing an increased number of adapter circuit boards with target machine emulation capabilities |
Karl N. Walker |
1992-08-11 |