Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847891 | System and method for detecting reuse of an existing known high-speed serial interconnect link | David Wyatt, Vishal Mehta, Michael Hopgood, Hitendra Dutt, Samuel Vincent +1 more | 2017-12-19 |
| 9250897 | Systems and methods that facilitate management of add-on instruction generation, selection, and/or monitoring during execution | James Harry Jarrett, John E. Belcher, Russell W. Brandes, Jeffery W. Brooks, Bruce A. Christensen +6 more | 2016-02-02 |
| 8949497 | Method and apparatus for interleaving bursts of high-speed serial interconnect link training with bus data transactions | Michael Hopgood, Wei-Je Huang, Hitendra Dutt, David Wyatt, Vishal Mehta | 2015-02-03 |
| 8393004 | Systems and methods for protecting information used by mobile devices | Wael Ibrahim | 2013-03-05 |
| 8365145 | Systems and methods that facilitate management of add-on instruction generation, selection, and/or monitoring during execution | James Harry Jarrett, John E. Belcher, Russell W. Brandes, Jeffery W. Brooks, Bruce A. Christensen +6 more | 2013-01-29 |
| 7680900 | Publish/subscribe messaging system | John J. Duigenan, Graham Derek Wallis | 2010-03-16 |
| 7457671 | Systems and methods that facilitate management of add-on instruction generation, selection, and/or monitoring during execution | James Harry Jarrett, John E. Belcher, Russell W. Brandes, Jeffery W. Brooks, Bruce A. Christensen +6 more | 2008-11-25 |
| 7412493 | Publish/subscribe messaging system | John J. Duigenan, Graham Derek Wallis | 2008-08-12 |
| 6125449 | Controlling power states of a computer | Larry W. Kunkel, Gokalp Bayramoglu, Henry M. D'Souza, Valiuddin Y. Ali | 2000-09-26 |
| 6076133 | Computer interface with hardwire button array | James W. Brainard, Larry W. Kunkel, Stephen A. Walsh, Michael A. Provencher | 2000-06-13 |
| 6018620 | Double buffering operations between the memory bus and the expansion bus of a computer system | Paul R. Culley | 2000-01-25 |
| 5987537 | Function selector with external hard wired button array on computer chassis that generates interrupt to system processor | James W. Brainard, Larry W. Kunkel, Stephen A. Walsh, Michael A. Provencher | 1999-11-16 |
| 5966301 | Redundant processor controller providing upgrade recovery | William B. Cook, Mark A. Flood, Steven P. Richter, Bradley J. Bittorf | 1999-10-12 |
| 5966300 | Redundant automation controller with deductive power-up | Mark A. Flood, William B. Cook, Steven P. Richter | 1999-10-12 |
| 5966304 | Redundant automation controller permitting replacement of components during operation | William B. Cook, Mark A. Flood | 1999-10-12 |
| 5963448 | Industrial controller having redundancy and using connected messaging and connection identifiers to enable rapid switchover without requiring new connections to be opened or closed at switchover | Mark A. Flood | 1999-10-05 |
| 5870568 | Double buffering operations between the memory bus and the expansion bus of a computer system | Paul R. Culley | 1999-02-09 |
| 5870602 | Multi-processor system with system wide reset and partial system reset capabilities | David A. Miller, Kenneth A. Jansen, Paul R. Culley, Javier F. Izquierdo | 1999-02-09 |
| 5751998 | Memory accessing system with portions of memory being selectively write protectable and relocatable based on predefined register bits and memory selection RAM outputs | Russell J. Wunderlich, Charles J. Stancil, Mikal C. Hunsaker, Brian V. Belmont | 1998-05-12 |
| 5737604 | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | David A. Miller, Kenneth A. Jansen, Paul R. Culley, Javier F. Izquierdo | 1998-04-07 |
| 5611078 | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | David A. Miller, Kenneth A. Jansen, Paul R. Culley, Javier F. Izquierdo | 1997-03-11 |
| 5553310 | Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems | Paul R. Culley, Maria L. Melo, Roger E. Tipley | 1996-09-03 |
| 5535395 | Prioritization of microprocessors in multiprocessor computer systems | Roger E. Tipley, Michael Moriarty | 1996-07-09 |
| 5519839 | Double buffering operations between the memory bus and the expansion bus of a computer system | Paul R. Culley | 1996-05-21 |
| 5465360 | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | David A. Miller, Kenneth A. Jansen, Paul R. Culley, Javier F. Izquierdo | 1995-11-07 |