| 6357013 |
Circuit for setting computer system bus signals to predetermined states in low power mode |
Philip C. Kelly, James R. Reif |
2002-03-12 |
| 6230227 |
Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridge |
Walter G. Fry, James R. Reif |
2001-05-08 |
| 6226700 |
Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices |
Shaun Wandler, Jeffrey C. Stevens, Jeff W. Wolford, Robert L. Woods, Danny Higby +2 more |
2001-05-01 |
| 6212590 |
Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base |
Maria L. Melo, Jeffrey Wilson |
2001-04-03 |
| 6199134 |
Computer system with bridge logic that asserts a system management interrupt signal when an address is made to a trapped address and which also completes the cycle to the target address |
Russ Wunderlich |
2001-03-06 |
| 6199131 |
Computer system employing optimized delayed transaction arbitration technique |
Maria L. Melo, Khaldoun Alzien |
2001-03-06 |
| 6145029 |
Computer system with enhanced docking support |
Paul Stanley |
2000-11-07 |
| 6101566 |
Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices |
Robert L. Woods, Jeff W. Wolford, Jeffrey C. Stevens, Shaun Wandler, Jeffrey Wilson +2 more |
2000-08-08 |
| 6094700 |
Serial bus system for sending multiple frames of unique data |
David J. DeLisle, Russ Wunderlich |
2000-07-25 |
| 6070215 |
Computer system with improved transition to low power operation |
Robert C. Elliott |
2000-05-30 |
| 6065122 |
Smart battery power management in a computer system |
Russ Wunderlich, Kamran Khederzadeh |
2000-05-16 |
| 5991833 |
Computer system with bridge logic that reduces interference to CPU cycles during secondary bus transactions |
Shaun Wandler, Maria L. Melo |
1999-11-23 |
| 5987555 |
Dynamic delayed transaction discard counter in a bus bridge of a computer system |
Khaldoun Alzien, Maria L. Melo |
1999-11-16 |
| 5796992 |
Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode |
James R. Reif, Michael J. Collins |
1998-08-18 |
| 5740454 |
Circuit for setting computer system bus signals to predetermined states in low power mode |
Philip C. Kelly, James R. Reif |
1998-04-14 |
| 5721935 |
Apparatus and method for entering low power mode in a computer system |
James R. Reif, James R. Edwards, Michael J. Collins, John E. Larson |
1998-02-24 |