Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5966728 | Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device | Nader Amini, Bechara F. Boury, Sherwood Brannon | 1999-10-12 |
| 5761533 | Computer system with varied data transfer speeds between system components and memory | Alfredo Aldereguia, Nader Amini, Daryl Cromer, Ashu Kohli, Kimberly K. Sendlein +1 more | 1998-06-02 |
| 5673414 | Snooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O device | Nader Amini, Bechara F. Boury, Sherwood Brannon | 1997-09-30 |
| 5659696 | Method and apparatus for determining address location and taking one of two actions depending on the type of read/write data transfer required | Nader Amini | 1997-08-19 |
| 5644729 | Bidirectional data buffer for a bus-to-bus interface unit in a computer system | Nader Amini, Bechara F. Boury, Sherwood Brannon, Terence J. Lohman | 1997-07-01 |
| 5544346 | System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus | Nader Amini, Bechara F. Boury, Sherwood Brannon, Terence J. Lohman | 1996-08-06 |
| 5313627 | Parity error detection and recovery | Nader Amini, Bechara F. Boury, Sherwood Brannon | 1994-05-17 |
| 5265211 | Arbitration control logic for computer system having dual bus architecture | Nader Amini, Bechara F. Boury, Terence J. Lohman | 1993-11-23 |
| 5255374 | Bus interface logic for computer system having dual bus architecture | Alfredo Aldereguia, Nader Amini, Terence J. Lohman, Cang Ngoc Tran | 1993-10-19 |