TL

Terence J. Lohman

IBM: 15 patents #7,450 of 70,183Top 15%
QU Qualcomm: 7 patents #2,597 of 12,104Top 25%
📍 Boca Raton, FL: #96 of 2,373 inventorsTop 5%
🗺 Florida: #2,045 of 67,251 inventorsTop 4%
Overall (All Time): #197,222 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Showing 1–22 of 22 patents

Patent #TitleCo-InventorsDate
8880829 Method and apparatus for efficient, low-latency, streaming memory copies Gregory A. Reid, Brent L. DeGraaf 2014-11-04
8675679 Cooperative writes over the address channel of a bus Richard Gerard Hofmann 2014-03-18
8521914 Auxiliary writes over address channel Richard Gerard Hofmann 2013-08-27
8107492 Cooperative writes over the address channel of a bus Richard Gerard Hofmann 2012-01-31
8108563 Auxiliary writes over address channel Richard Gerard Hofmann 2012-01-31
7822903 Single bus command having transfer information for transferring data in a processing system Richard Gerard Hofmann 2010-10-26
7249210 Bus access arbitration scheme Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann 2007-07-24
5644729 Bidirectional data buffer for a bus-to-bus interface unit in a computer system Nader Amini, Bechara F. Boury, Sherwood Brannon, Richard Louis Horne 1997-07-01
5621897 Method and apparatus for arbitrating for a bus to enable split transaction bus protocols Bechara F. Boury, Charles Edward Kuhlmann, Neil W. Songer, Ronald Valli 1997-04-15
5615217 Boundary-scan bypass circuit for integrated circuit electronic component and circuit boards incorporating such circuits and components Rick L. Horne, Mark G. Noll, Jose A. Olive, Roberto V. Perez 1997-03-25
5555413 Computer system and method with integrated level and edge interrupt requests at the same interrupt priority Mark G. Noll, Jose A. Olive, Roberto V. Perez 1996-09-10
5551009 Expandable high performance FIFO design which includes memory cells having respective cell multiplexors Nader Amini, Bechara E. Boury, Sherwood Brannon 1996-08-27
5548786 Dynamic bus sizing of DMA transfers Nader Amini, Bechara F. Boury, Sherwood Brannon, Ian A. Concilio, Richard Gerard Hofmann 1996-08-20
5544346 System having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a bus Nader Amini, Bechara F. Boury, Sherwood Brannon, Richard Louis Horne 1996-08-06
5450551 System direct memory access (DMA) support logic for PCI based computer system Nader Amini, Patrick M. Bland, Bechara F. Boury, Richard Gerard Hofmann 1995-09-12
5396602 Arbitration logic for multiple bus computer system Nader Amini, Patrick M. Bland, Bechara F. Boury, Richard Gerard Hofmann 1995-03-07
5381538 DMA controller including a FIFO register and a residual register for data buffering and having different operating modes Nader Amini, Bechara F. Boury 1995-01-10
5333274 Error detection and recovery in a DMA controller Nader Amini, Bechara F. Boury, Sherwood Brannon, Richard Gerard Hofmann 1994-07-26
5301282 Controlling bus allocation using arbitration hold Nader Amini, Bechara F. Boury 1994-04-05
5265211 Arbitration control logic for computer system having dual bus architecture Nader Amini, Bechara F. Boury, Richard Louis Horne 1993-11-23
5255374 Bus interface logic for computer system having dual bus architecture Alfredo Aldereguia, Nader Amini, Richard Louis Horne, Cang Ngoc Tran 1993-10-19
5239631 CPU bus allocation control Bechara F. Boury, Long D. Nguyen 1993-08-24