Issued Patents All Time
Showing 25 most recent of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12316349 | Iterative decoding technique for correcting DRAM device failures | Joseph M. McCrate, Mohammed Ebrahim Hargan | 2025-05-27 |
| 12210413 | Data correction scheme with reduced device overhead | Joseph M. McCrate, Marco Sforzin, Paolo Amato, Lingming Yang | 2025-01-28 |
| 12176029 | Drift aware read operations | Karthik Sarpatwari, Lingming Yang, John F. Schreck | 2024-12-24 |
| 12170531 | Iterative decoder for correcting dram device failures | Joseph M. McCrate, Mohammed Ebrahim Hargan | 2024-12-17 |
| 12106803 | Multi-step pre-read for write operations in memory devices | Yen-Chun Lee, Karthik Sarpatwari | 2024-10-01 |
| 12094533 | Memory cell read operation techniques | Riccardo Muzzetto, Francesco Mastroianni, Ferdinando Bedeschi | 2024-09-17 |
| 12080359 | Identify the programming mode of memory cells during reading of the memory cells | Karthik Sarpatwari, Fabio Pellizzer | 2024-09-03 |
| 12032443 | Shadow DRAM with CRC+RAID architecture, system and method for high RAS feature in a CXL drive | Sandeep Krishna Thirumala, Lingming Yang, Amitava Majumdar | 2024-07-09 |
| 12019516 | Instant write scheme with delayed parity/raid | Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala | 2024-06-25 |
| 12014784 | Evaluation of background leakage to select write voltage in memory devices | Karthik Sarpatwari, Zhongyuan Lu | 2024-06-18 |
| 12013756 | Method and memory system for writing data to dram submodules based on the data traffic demand | Lingming Yang, Amitava Majumdar, Sandeep Krishna Thirumala | 2024-06-18 |
| 11962327 | Iterative decoding technique for correcting DRAM device failures | Joseph M. McCrate, Mohammed Ebrahim Hargan | 2024-04-16 |
| 11942139 | Performing refresh operations on memory cells | Karthik Sarpatwari, Lingming Yang, John Christopher Sancon | 2024-03-26 |
| 11923007 | Dirty write on power off | Karthik Sarpatwari, Fabio Pellizzer, Jessica Chen | 2024-03-05 |
| 11894078 | Accessing a multi-level memory cell | Karthik Sarpatwari, Xuan Anh Tran, Jessica Chen, Jason A. Durand, Yen-Chun Lee | 2024-02-06 |
| 11875867 | Weighted wear leveling for improving uniformity | Zhongyuan Lu, Karthik Sarpatwari | 2024-01-16 |
| 11862226 | Systems and methods for pre-read scan of memory devices | Karthik Sarpatwari, Fabio Pellizzer, Yen-Chun Lee, Ferdinando Bedeschi | 2024-01-02 |
| 11783902 | Multi-state programming of memory cells | Karthik Sarpatwari | 2023-10-10 |
| 11782830 | Cache memory with randomized eviction | Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari | 2023-10-10 |
| 11775431 | Cache memory with randomized eviction | Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari | 2023-10-03 |
| 11728005 | Bipolar read retry | Yen-Chun Lee, Karthik Sarpatwari | 2023-08-15 |
| 11710528 | Data-based polarity write operations | Karthik Sarpatwari, Hongmei Wang, Mingdong Cui | 2023-07-25 |
| 11705197 | Modified write voltage for memory devices | Sandeepan Dasgupta, Sanjay Rangan, Koushik Banerjee, Mase J. Taub, Kiran Pangal | 2023-07-18 |
| 11694747 | Self-selecting memory cells configured to store more than one bit per memory cell | Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen +1 more | 2023-07-04 |
| 11688460 | Memory operation with double-sided asymmetric decoders | Fabio Pellizzer, John F. Schreck | 2023-06-27 |