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Interconnect to communicate information uni-directionally |
Shaun M. Conrad, William Knolla, SM Masudur Rahman, Jawad Haj-Yihia, Alon Naveh +1 more |
2017-09-19 |
| 9690353 |
System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request |
Achmed R. Zahir, William Knolla, Hartej Singh, Vasudev Bibikar, Sanjeev Jahagirdar +3 more |
2017-06-27 |
| 9477627 |
Interconnect to communicate information uni-directionally |
Shaun M. Conrad, William Knolla, SM Masudur Rahman, Jawad Haj-Yihia, Alon Naveh +1 more |
2016-10-25 |
| 9152205 |
Mechanism for facilitating faster suspend/resume operations in computing systems |
Ohad Falik, Eliezer Weissmann, Alon Naveh, Michael Mishaeli, Nadav Shulman +3 more |
2015-10-06 |
| 9098561 |
Determining an effective stress level on a processor |
Dorit Shapira, Efraim Rotem |
2015-08-04 |
| 9092632 |
Platform firmware armoring technology |
Allen R. Wishman, Sergiu D. Ghetie, Michael Neve de Mevergnies, Ulhas Warrier, Adil Karrar +1 more |
2015-07-28 |
| 8650427 |
Activity alignment algorithm by masking traffic flows |
William Knolla, Neil W. Songer |
2014-02-11 |
| 8522322 |
Platform firmware armoring technology |
Allen R. Wishman, Sergiu D. Ghetie, Michael Neve de Mevergnies, Ulhas Warrier, Adil Karrar +1 more |
2013-08-27 |
| 8145816 |
System and method for deadlock free bus protection of resources during search execution |
Stephen A. Fischer, James A. Sutton |
2012-03-27 |
| 7861024 |
Providing a set aside mechanism for posted interrupt transactions |
Bryan R. White |
2010-12-28 |
| 7610611 |
Prioritized address decoder |
Satish B. Acharya, Zohar Bogin, Sean G. Galloway |
2009-10-27 |
| 7139890 |
Methods and arrangements to interface memory |
Clifford D. Hall, Thomas A. Piazza, Richard W. Jensen |
2006-11-21 |
| 6738869 |
Arrangements for out-of-order queue cache coherency and memory write starvation prevention |
Thomas C. Brown, Kenneth B. Oliver |
2004-05-18 |
| 6618770 |
Graphics address relocation table (GART) stored entirely in a local memory of an input/output expansion bridge for input/output (I/O) address translation |
Raman Nayyar, Leonard W. Cross |
2003-09-09 |
| 6615374 |
First and next error identification for integrated circuit devices |
— |
2003-09-02 |
| 6594756 |
Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor |
Sham M. Datta, Mani Ayyar, Stephen S. Pawlowski |
2003-07-15 |
| 6457068 |
Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation |
Raman Nayyar, Leonard W. Cross |
2002-09-24 |
| 5278800 |
Memory system and unique memory chip allowing island interlace |
Warren W. Grunbok, Billy J. Knowles, William R. Milani, Dale E. Pontius, Donald W. Price +4 more |
1994-01-11 |
