Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6418496 | System and apparatus including lowest priority logic to select a processor to receive an interrupt message | Daniel G. Lau | 2002-07-09 |
| 6415367 | Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme | Brent S. Baxter | 2002-07-02 |
| 6412049 | Method for minimizing CPU memory latency while transferring streaming data | Brent S. Baxter, John I. Garney | 2002-06-25 |
| 6412060 | Method and apparatus for supporting multiple overlapping address spaces on a shared bus | Peter D. MacWilliams | 2002-06-25 |
| 6405271 | Data flow control mechanism for a bus supporting two-and three-agent transactions | Peter D. MacWilliams, Nitin V. Sarangdhar, Gurbir Singh | 2002-06-11 |
| 6401153 | Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals | — | 2002-06-04 |
| 6381665 | Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals | — | 2002-04-30 |
| 6374321 | Mechanisms for converting address and data signals to interrupt message signals | Darren Abramson, David I. Poisner, Kishore Mishra | 2002-04-16 |
| 6363461 | Apparatus for memory resource arbitration based on dedicated time slot allocation | Brent S. Baxter | 2002-03-26 |
| 6263397 | Mechanism for delivering interrupt messages | William S. Wu, Mani Azimi, Daniel G. Lau, M. Jayakumar | 2001-07-17 |
| 6253302 | Method and apparatus for supporting multiple overlapping address spaces on a shared bus | Peter D. MacWilliams | 2001-06-26 |
| 6219741 | Transactions supporting interrupt destination redirection and level triggered interrupt semantics | Daniel G. Lau, Kimberly C. Weier | 2001-04-17 |
| 6195712 | Dynamic discovery of wireless peripherals | Mohan J. Kumar, David E. Ackelson | 2001-02-27 |
| 6178206 | Method and apparatus for source synchronous data transfer | Timothy Kelly, Keith Self, Jeffrey E. Smith | 2001-01-23 |
| 6151663 | Cluster controller for memory and data cache in a multiple cluster processing system | Tom Holman | 2000-11-21 |
| 6108735 | Method and apparatus for responding to unclaimed bus transactions | — | 2000-08-22 |
| 6012118 | Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus | Muthurajan Jayakumar, Sunny C. Huang, Peter D. MacWilliams, William S. Wu, Bindi A. Prasad | 2000-01-04 |
| 5996042 | Scalable, high bandwidth multicard memory system utilizing a single memory controller | Peter D. MacWilliams | 1999-11-30 |
| 5978737 | Method and apparatus for hazard detection and distraction avoidance for a vehicle | Andrew F. Glew, George R. Hayek, Harshvardhan Sharangpani, Richard Calderwood | 1999-11-02 |
| 5961621 | Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system | William S. Wu, Peter D. MacWilliams, Muthurajan Jayakumar | 1999-10-05 |
| 5956516 | Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals | — | 1999-09-21 |
| 5923857 | Method and apparatus for ordering writeback data transfers on a bus | Peter D. MacWilliams, Nitin V. Sarangdhar, Gurbir Singh | 1999-07-13 |
| 5919254 | Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system | Peter D. MacWilliams, William S. Wu, Len Schultz | 1999-07-06 |
| 5911053 | Method and apparatus for changing data transfer widths in a computer system | Peter D. MacWilliams, Gurbir Singh | 1999-06-08 |
| 5905876 | Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system | Peter D. MacWilliams, D. Michael Bell | 1999-05-18 |