Issued Patents All Time
Showing 51–67 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5906001 | Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines | William S. Wu, Peter D. MacWilliams | 1999-05-18 |
| 5903916 | Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation | Peter D. MacWilliams, Sridhar Lakshmanamurthy | 1999-05-11 |
| 5848279 | Mechanism for delivering interrupt messages | William S. Wu, Mani Azimi, Daniel G. Lau, Muthurajan Jayakumar | 1998-12-08 |
| 5829052 | Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system | Tom Holman | 1998-10-27 |
| 5812803 | Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller | Patrick F. Stolt | 1998-09-22 |
| 5796977 | Highly pipelined bus architecture | Nitin V. Sarangdhar, Gurbir Singh, Konrad K. Lai, Peter D. MacWilliams, Michael W. Rhodehamel | 1998-08-18 |
| 5784579 | Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth | Nitin V. Sarangdhar, Michael W. Rhodehamel, Matthew A. Fisch, Peter D. MacWilliams | 1998-07-21 |
| 5696910 | Method and apparatus for tracking transactions in a pipelined bus | — | 1997-12-09 |
| 5615343 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Michael W. Rhodehamel | 1997-03-25 |
| 5550533 | High bandwidth self-timed data clocking scheme for memory bus implementation | — | 1996-08-27 |
| 5548734 | Equal length symmetric computer bus topology | Jerzy Kolinski, John T. Sprietsma, Henry Schaechterle | 1996-08-20 |
| 5537640 | Asynchronous modular bus architecture with cache consistency | Peter D. MacWilliams, David Cowan, Howard S. David | 1996-07-16 |
| 5513331 | Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset | Peter D. MacWilliams | 1996-04-30 |
| 5471637 | Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer | Peter D. MacWilliams, Jerzy Kolinski | 1995-11-28 |
| 5455957 | Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol | Peter D. MacWilliams | 1995-10-03 |
| 5301299 | Optimized write protocol for memory accesses utilizing row and column strobes | Peter D. MacWilliams | 1994-04-05 |
| 5239638 | Two strobed memory access | Peter D. MacWilliams | 1993-08-24 |