Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10048966 | Instruction set for supporting wide scalar pattern matches | Hariharan Lakshminarayanan Thantry | 2018-08-14 |
| 9674114 | Modular decoupled crossbar for on-chip router | Dongkook Park, Aniruddha Vaidya, Akhilesh Kumar | 2017-06-06 |
| 9606797 | Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor | Aniruddha Vaidya, Anahita Shayesteh, Dong Hyuk Woo, Saikat Saharoy | 2017-03-28 |
| 9542186 | Instruction set for supporting wide scalar pattern matches | Hariharan Lakshminarayanan Thantry | 2017-01-10 |
| 9424191 | Scalable coherence for multi-core processors | Naveen Cherukuri | 2016-08-23 |
| 9424031 | Techniques for enabling bit-parallel wide string matching with a SIMD register | Hariharan Lakshminarayanan Thantry | 2016-08-23 |
| 9418011 | Region based technique for accurately predicting memory accesses | Livio B. Soares, Naveen Cherukuri, Akhilesh Kumar | 2016-08-16 |
| 9152419 | Instruction set for supporting wide scalar pattern matches | Hariharan Lakshminarayanan Thantry | 2015-10-06 |
| 8990506 | Replacing cache lines in a cache memory based at least in part on cache coherency state information | Naveen Cherukuri, Dennis W. Brzezinski, Ioannis T. Schoinas, Anahita Shayesteh, Akhilesh Kumar | 2015-03-24 |
| 8683136 | Apparatus and method for improving data prefetching efficiency using history based prefetching | Naveen Cherukuri | 2014-03-25 |
| 6263397 | Mechanism for delivering interrupt messages | William S. Wu, Stephen S. Pawlowski, Daniel G. Lau, M. Jayakumar | 2001-07-17 |
| 5848279 | Mechanism for delivering interrupt messages | William S. Wu, Stephen S. Pawlowski, Daniel G. Lau, Muthurajan Jayakumar | 1998-12-08 |