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USPTO Patent Rankings Data through Dec 31, 2025
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Muthurajan Jayakumar — 15 Patents

Intel: 15 patents #2,763 of 30,777Top 9%
Folsom, CA: #164 of 1,500 inventorsTop 15%
California: #40,789 of 386,348 inventorsTop 15%
Overall (All Time): #307,048 of 4,157,543Top 8%
15 Patents All Time
Muthurajan Jayakumar has been granted 15 US patents while listed as an inventor at Intel. The first was granted in 1996 and the most recent in September 2009. Muthurajan Jayakumar ranks #307,048 of 4,157,543 US inventors in our database (top 7.4%). Patent records list Muthurajan Jayakumar in Folsom, CA, US.

Issued Patents All Time

Showing 1–15 of 15 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
RE40921 Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system William S. Wu, Peter D. MacWilliams, Stephen S. Pawlowski 2009-09-22
6298410 Apparatus and method for initiating hardware priority management by software controlled register access Vijay Kumar Goru, Ravi Eakambaram 2001-10-02 $98,303,000
6292906 Method and apparatus for detecting and compensating for certain snoop errors in a system with multiple agents having cache memories John Fu 2001-09-18 $133,519,000
6260091 Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred reply Sunny C. Huang 2001-07-10 $188,222,000
6108781 Bootstrap processor selection architecture in SMP system 2000-08-22 $235,703,000
6021458 Method and apparatus for handling multiple level-triggered and edge-triggered interrupts Vijay Kumar Goru 2000-02-01 $155,838,000
6012118 Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus Sunny C. Huang, Peter D. MacWilliams, William S. Wu, Stephen S. Pawlowski, Bindi A. Prasad 2000-01-04 $201,443,000
5964856 Mechanism for data strobe pre-driving during master changeover on a parallel bus William S. Wu, Leonard Joshua Schultz, Dilip K. Sampath, Bindi A. Prasad 1999-10-12 $143,616,000
5961621 Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system William S. Wu, Peter D. MacWilliams, Stephen S. Pawlowski 1999-10-05 $132,199,000
5951663 Method and apparatus for tracking bus transactions William S. Wu, Len Schultz 1999-09-14 $149,288,000
5904733 Bootstrap processor selection architecture in SMP systems 1999-05-18 $162,962,000
5889978 Emulation of interrupt control mechanism in a multiprocessor system 1999-03-30 $45,277,000
5848279 Mechanism for delivering interrupt messages William S. Wu, Mani Azimi, Stephen S. Pawlowski, Daniel G. Lau 1998-12-08 $117,934,000
5511200 Method and apparatus for providing an enhanced programmable priority interrupt controller 1996-04-23 $71,963,000
5481725 Method for providing programmable interrupts for embedded hardware used with programmable interrupt controllers Ronald L. Mosgrove, Hugh Bynum 1996-01-02 $94,165,000