| RE40921 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system |
William S. Wu, Peter D. MacWilliams, Stephen S. Pawlowski |
2009-09-22 |
| 6298410 |
Apparatus and method for initiating hardware priority management by software controlled register access |
Vijay Kumar Goru, Ravi Eakambaram |
2001-10-02 |
| 6292906 |
Method and apparatus for detecting and compensating for certain snoop errors in a system with multiple agents having cache memories |
John Fu |
2001-09-18 |
| 6260091 |
Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred reply |
Sunny C. Huang |
2001-07-10 |
| 6108781 |
Bootstrap processor selection architecture in SMP system |
— |
2000-08-22 |
| 6021458 |
Method and apparatus for handling multiple level-triggered and edge-triggered interrupts |
Vijay Kumar Goru |
2000-02-01 |
| 6012118 |
Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus |
Sunny C. Huang, Peter D. MacWilliams, William S. Wu, Stephen S. Pawlowski, Bindi A. Prasad |
2000-01-04 |
| 5964856 |
Mechanism for data strobe pre-driving during master changeover on a parallel bus |
William S. Wu, Leonard Joshua Schultz, Dilip K. Sampath, Bindi A. Prasad |
1999-10-12 |
| 5961621 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system |
William S. Wu, Peter D. MacWilliams, Stephen S. Pawlowski |
1999-10-05 |
| 5951663 |
Method and apparatus for tracking bus transactions |
William S. Wu, Len Schultz |
1999-09-14 |
| 5904733 |
Bootstrap processor selection architecture in SMP systems |
— |
1999-05-18 |
| 5889978 |
Emulation of interrupt control mechanism in a multiprocessor system |
— |
1999-03-30 |
| 5848279 |
Mechanism for delivering interrupt messages |
William S. Wu, Mani Azimi, Stephen S. Pawlowski, Daniel G. Lau |
1998-12-08 |
| 5511200 |
Method and apparatus for providing an enhanced programmable priority interrupt controller |
— |
1996-04-23 |
| 5481725 |
Method for providing programmable interrupts for embedded hardware used with programmable interrupt controllers |
Ronald L. Mosgrove, Hugh Bynum |
1996-01-02 |