Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for handling multiple level-triggered and edge-triggered interrupts

Method and apparatus for handling multiple level-triggered and edge-triggered interrupts

US Patent 6021458 · Granted Feb 1, 2000

Estimated economic value: $155,838,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Mechanism for efficiently processing deferred order-dependent memory access tran2009
Apparatus and method for initiating hardware priority management by software con2001
Apparatus and method for initiating hardware priority management by software con2001
Method and apparatus for detecting and compensating for certain snoop errors in 2001
Method and apparatus for performing out-of-order bus operations in which an agen2001
Method and apparatus for processing more than one interrupts without reinitializ2000
Bootstrap processor selection architecture in SMP system2000
Method and apparatus for performing bus operations in a computer system using de2000
Mechanism for data strobe pre-driving during master changeover on a parallel bus1999
Mechanism for efficiently processing deferred order-dependent memory access tran1999
Method and apparatus for tracking bus transactions1999
Bootstrap processor selection architecture in SMP systems1999