Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7535918 | Copy on access mechanisms for low latency data movement | Anil Vasudevan, Sujoy Sen, Parthasarathy Sarangam | 2009-05-19 |
| 7480747 | Method and apparatus to reduce latency and improve throughput of input/output data in a processor | Anil Vasudevan | 2009-01-20 |
| 7107371 | Method and apparatus for providing and embedding control information in a bus system | — | 2006-09-12 |
| 7016989 | Fast 16 bit, split transaction I/O bus | — | 2006-03-21 |
| 6330630 | Computer system having improved data transfer across a bus bridge | — | 2001-12-11 |
| 6317799 | Destination controlled remote DMA engine | William T. Futral | 2001-11-13 |
| 6266778 | Split transaction I/O bus with pre-specified timing protocols to synchronously transmit packets between devices over multiple cycles | — | 2001-07-24 |
| 6148356 | Scalable computer system | David W. Archer, Doug Moran, Steve Pawlowski | 2000-11-14 |
| 6134622 | Dual mode bus bridge for computer system | Suvansh Krishan Kapur, Kevin Koschoreck, Srinand Venkatesan | 2000-10-17 |
| 6108736 | System and method of flow control for a high speed bus | — | 2000-08-22 |
| 6088370 | Fast 16 bit, split transaction I/O bus | — | 2000-07-11 |
| 6081851 | Method and apparatus for programming a remote DMA engine residing on a first bus from a destination residing on a second bus | William T. Futral | 2000-06-27 |
| 6070207 | Hot plug connected I/O bus for computer system | — | 2000-05-30 |
| 6047120 | Dual mode bus bridge for interfacing a host bus and a personal computer interface bus | — | 2000-04-04 |
| 6021451 | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge | Mark A. Gonzales, Susan S. Meredith | 2000-02-01 |
| 5905876 | Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system | Stephen S. Pawlowski, Peter D. MacWilliams | 1999-05-18 |
| 5835739 | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge | Mark A. Gonzales, Susan S. Meredith | 1998-11-10 |
| 5828865 | Dual mode bus bridge for interfacing a host bus and a personal computer interface bus | — | 1998-10-27 |
| 5594882 | PCI split transactions utilizing dual address cycle | — | 1997-01-14 |
| 5546546 | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge | Mark A. Gonzales, Susan S. Meredith | 1996-08-13 |
| 5535340 | Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge | Mark A. Gonzales, Susan S. Meredith | 1996-07-09 |
| 5434996 | Synchronous/asynchronous clock net with autosense | — | 1995-07-18 |
| 5410707 | Bootstrap loading from external memory including disabling a reset from a keyboard controller while an operating system load signal is active | — | 1995-04-25 |