Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9552032 | Branch prediction power reduction | Aneesh Aggarwal, Ross Segelken, Paul Wasson | 2017-01-24 |
| 9396117 | Instruction cache power reduction | Aneesh Aggarwal, Ross Segelken | 2016-07-19 |
| 7945803 | Clock generation for multiple clock domains | Anthony Mark Jones | 2011-05-17 |
| 6134622 | Dual mode bus bridge for computer system | Suvansh Krishan Kapur, Srinand Venkatesan, D. Michael Bell | 2000-10-17 |