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Method to prefetch data from system memory using a bus interface unit |
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Method and apparatus of bus interface for a processor |
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Computer system having a bus interface unit for prefetching data from system memory |
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2002-09-17 |
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Method and apparatus for data and address transmission over a bus |
David Gray, Linda J. Rankin |
2002-06-25 |
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Method and apparatus for automatically scrubbing ECC errors in memory via hardware |
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2000-08-08 |
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Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
D. Michael Bell, Susan S. Meredith |
2000-02-01 |
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CPU reads data from slow bus if I/O devices connected to fast bus do not acknowledge to a read request after a predetermined time interval |
David Gray, Linda J. Rankin |
1999-04-27 |
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Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
D. Michael Bell, Susan S. Meredith |
1998-11-10 |
| 5546546 |
Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
D. Michael Bell, Susan S. Meredith |
1996-08-13 |
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Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge |
D. Michael Bell, Susan S. Meredith |
1996-07-09 |
| 5471601 |
Memory device and method for avoiding live lock of a DRAM with cache |
— |
1995-11-28 |
| 5455939 |
Method and apparatus for error detection and correction of data transferred between a CPU and system memory |
Linda J. Rankin |
1995-10-03 |
| 5261109 |
Distributed arbitration method and apparatus for a computer bus using arbitration groups |
Sudarshan B. Cadambi, Charles B. Guy, David Gray |
1993-11-09 |
| 5191649 |
Multiprocessor computer system with data bus and ordered and out-of-order split data transactions |
Sudarshan B. Cadambi, Charles B. Guy, David Gray |
1993-03-02 |
